A crucial step in the manufacture of semiconductor integrated circuits is the testing of those circuits at various stages in their manufacture. As integrated circuits become more complex and require more pins for interconnection to circuit boards and the like, the problems of testing those circuits increase dramatically.
A substantial problem in the testing of high pin count integrated circuits is the size of the test head required. Current state of the art automated testers dedicate a forcing and measuring unit which is capable of imposing a number of force conditions and measuring responses, to each pin of the device under test. In order to eliminate signal degradation and other problems it is necessary to locate these force and measure units as close to the pin under test as possible. Therefore, as more capabilities are designed into the force and measure units and the testers are designed to test more pins, the physical size of the test head quickly increases to unmanageable proportions. All of these problems are exacerbated by the increase in speed of current state of the art testers. The resulting high switching rates of the test head make problems of interference and signal quality much more troublesome.